1. Technical Field
The present invention relates to a semiconductor memory device such as DRAM and a method for fabricating the device.
2. Related Art
DRAM of the capacitor-under-bitline (CUB) structure, in which capacitance elements for charge storage are arranged under bit lines, uses concave-type capacitance electrodes. Use of concave-type capacitance electrodes for DRAM is said to be advantageous for refining in that the surface of an interlayer insulating film formed over the DRAM can be made flat.
The structure of a DRAM-embedded semiconductor device with conventional concave-type capacitance electrodes will be described below in conjunction with FIGS. 17A and 17B. FIG. 17A is a plan view of a conventional DRAM-embedded semiconductor device, showing the structure thereof. FIG. 17B is a cross section of the semiconductor device taken along the line XVIIb-XVIIb shown in FIG. 17A.
As shown in FIG. 17B, on a silicon substrate 101, a shallow trench isolation (STI) 102 is formed to surround a region in which a transistor is formed. Over the silicon substrate 101 is formed a gate electrode 103 across a gate insulating film (not shown). An interlayer insulating layer 104 is formed on the silicon substrate 101 and the gate electrode 103. A contact plug 105 is formed in the interlayer insulating film 104 to reach the silicon substrate 101. Over the interlayer insulating film 104 are formed a silicon nitride film 106 and an interlayer insulating film 107. A capacitance cell hole (capacitor opening portion 116) is formed through the interlayer insulating film 107 to reach the surface of the contact plug 105.
A capacitance element is composed of a lower electrode 108 covering the bottom and sides of the capacitor opening portion 116, a capacitance insulating film 109 covering the capacitance opening portion 116 and part of the interlayer insulating film 107, and an upper electrode 110 covering the upper surface of the capacitance insulating film 109. An interlayer insulating film 112 is formed on the upper electrode 110. A bit-line contact plug 113 is formed through the interlayer insulating films 112 and 107 to reach the contact plug 105. On the interlayer insulating film 112 is formed a bit line 114 to be connected to the bit-line contact plug 113.
The capacitance element of the semiconductor device shown in FIGS. 17A and 17B is formed in the following manner. First, the lower electrode 108 is formed on the bottom and sides of the capacitor opening portion 116, and thereafter the capacitance insulating film 109 and the upper electrode 110 are formed over the interlayer insulating film 107 including the capacitor opening portion 116. Then, the upper electrode 110 is etched using a resist mask, and an opening portion 115 for forming the bit-line contact plug 113 therethrough is formed through the upper electrode 110.
The opening portion 115 is provided while securing a predetermined margin al relative to the bit-line contact plug 113 and a predetermined margin a2 relative to a capacitor opening portion 116. That is, the predetermined margin al is set considering mis-alignment of a photo mask for forming the bit-line contact plug 113, and the predetermined margin a2 is set considering mis-alignment of a photo resist mask for forming the capacitor opening portion 116.